@article {Bhardwaj:August 2006:1546-1998:240,
	author = "Bhardwaj, Sarvesh",
	author = "Cao, Yu",
	author = "Vrudhula, Sarma",
	title = "Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection",
	journal = "Journal of Low Power Electronics",
	volume = "2",
	year = "August 2006",
	abstract = "This paper proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on <I>&#945;</I>-percentile of the path delays using physical delay models fitted to a 90-nm industrial technology. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The formulated leakage minimization problem is shown to be a <I>multivariable convex optimization</I> problem under specific variable transformations. We demonstrate that our statistical optimization can lead to more than 50% reduction in the 90-percentile leakage for a 6% increase in the required time constraint.",
	pages = "240-250(11)",
	url = "http://www.ingentaconnect.com/content/asp/jolpe/2006/00000002/00000002/art00010"
	doi = "doi:10.1166/jolpe.2006.065"
}